Caracteristicas y Especificaciones de:

Kingston DDR3 2Gb 1066MHz ValueRAM CL7 1 CARA

Modelo: KVR1066D3S8N7/2G  Stock: 1-9

Precio de Venta

12.90 €

Portes 24-48 horas

3.99 €

Seguro de transporte e IVA incluidos.

KVR1066D3S8N7/2G
2GB 1Rx8 256M x 64-Bit PC3-8500
CL7 240-Pin DIMM    

DESCRIPTION
This document describes ValueRAM's 256M x 64-bit (2GB)
DDR3-1066 CL7 SDRAM (Synchronous DRAM), 1Rx8 memory
module, based on eight 256M x 8-bit DDR3-1066 FBGA components.
The SPD is programmed to JEDEC standard latency
DDR3-1066 timing of 7-7-7 at 1.5V. This 240-pin DIMM uses
gold contact fingers. The electrical and mechanical specifications
are as follows:

FEATURES
- JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
- VDDQ = 1.5V (1.425V ~ 1.575V)
- 533MHz fCK for 1066Mb/sec/pin
- 8 independent internal bank
- Programmable CAS Latency: 9, 8, 7, 6
- Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
- Programmable CAS Write Latency(CWL) = 6 (DDR3-1066)
- 8-bit pre-fetch
- Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
- Bi-directional Differential Data Strobe
- Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
- On Die Termination using ODT pin
- Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
- Asynchronous Reset
- PCB Height: 1.18” (30mm), single sided component
*Power will vary depending on the SDRAM used.

SPECIFICATIONS
CL(IDD) 7 cycles
Row Cycle Time (tRCmin) 50.63ns (min.)
Refresh to Active/Refresh 160ns (min.)
Command Time (tRFCmin)
Row Active Time (tRASmin) 37.5ns (min.)
Power (Operating) 0.725 W*
UL Rating 94 V - 0
Operating Temperature 0o C to 85o C
Storage Temperature -55o C to +100o C
Continued >>
Important Information: The module defined in this data sheet is one of several configurations available under
this part number. While all configurations are compatible, the DRAM combination and/or the module height may
vary from what is described here.